In the world of computers and processors there is an unrelenting drive for additional computing power and faster calculation times. In this context, then, systems in which several processors can be combined to work in parallel with one another are necessary.
Imaging systems which obtain visual images and perform various manipulations with respect to the data and then control the display of the imaged and stored data inherently require large amounts of computations and memory. Such imaging systems are prime candidates for multi-processing where different processors perform different tasks concurrently in parallel. These processors can be working together in the single instruction, multiple data mode (SIMD) where all of the processors are operating from the same instruction stream but obtaining data from various sources, or the processors can be working together in the multiple instruction, multiple data mode (MIMD) where each processor is working from a different set of instructions and working on data from different sources. For different operations, different configurations are necessary.
Processors operate from a cache of instructions stored in a memory. If several processors had to queue for the same memory, the time savings achieved by multi-processors would be lost. Thus, in order to avoid such queueing problems when the system is operating in the MIMD mode, each processor requires a separate instruction memory.
However, when the system is operating in the SIMD mode, several processors are working from the same single instruction stream, thus freeing those memories that had been dedicated to providing separate instruction sets to the several parallel processors. Since memory capacity is always at a premium in complex systems, particularly in imaging systems, it is highly desirable to be able to convert the MIMD mode dedicated instruction cache memory to regularly addressable RAM memory when the system is operating in the SIMD mode.
It is thus desirable to establish a memory arrangement for a multi-processing system such that the memories function in one mode when the processors are operating from independent instructions and in a second mode when the processors are sharing instructions.
It is further desirable to provide a system which has different addressable memory spaces depending upon the processor mode of operation.
One method of solving the huge interconnection problem in complex systems such as the image processing system shown in one embodiment of the invention is to construct the entire processor as a single device. Conceptually this might appear easy to achieve, but in reality the problems are complicated.
First of all, an architecture must be created which allows for the efficient movement of information while at the same time conserving precious silicon chip space. The architecture must allow a very high degree of flexibility since once fabricated, it cannot easily be modified for different applications. Also, since the processing capability of the system will be high, there is a need for high band width in the movement of information on and off the chip. This is so since the physical number of leads which can attach to any one chip is limited.
It is also desirable to design an entire parallel processor system, such as an image processor, on a single silicon chip while maintaining the system flexible enough to satisfy wide ranging and constantly changing operational criteria.
It is further desirable to construct such a single chip parallel processor system where the processor memory interface is easily adaptable to operation in various modes, such as SIMD and MIMD, as well as adaptable to efficient on-off chip data communications.